1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a process for forming a multi-layer wiring.
2. Description of Related Art
In a typical conventional process of manufacturing a semiconductor device, a multi-layer wiring formation using a plating method has been performed for example as follows:
A lower level wiring conductor is formed on a field insulator film formed on a semiconductor substrate, and then, an interlayer insulating film is formed. Thereafter, a through hole is formed for connecting between the lower level wiring conductor and a possible upper level wiring conductor. In the case of an electroplating, a conducting film is formed as an electric current supplying layer.
In addition, a photoresist is coated on the conducting film, and then, patterned into a desired shape by a photolithography. By the electroplating process, an upper level wiring conductor is formed on a portion of the conducting film that is not covered by the photoresist.
Thereafter the photoresist is removed, and an exposed portion of the conducting film is removed, so that a desired wiring conductor is obtained.
In the above mentioned conventional multi-layer wiring forming process using the electroplating, the shape of the upper level wiring conductor becomes concave or recessed to reflect the shape of the lower level wiring conductor and the shape of the through hole portion for connecting between the upper level wiring conductor and the lower level wiring conductor. Therefore, if the number of the conductor levels becomes large in the multilayer wiring structure, it becomes difficult to planarize, and in addition, it is also difficult to form a wiring conductor in the uppermost level.